Design and Optimization of Sense Amplifier-Based Flip-Flops
نویسندگان
چکیده
Abstract An improved design of a sense amplifier-based flip-flop is presented. The new design overcomes the problems of floating nodes, which is a weakness of previously reported solutions. This is achieved by systematic derivation of flip-flop equations and rearranging the resulting network. The resulting flip-flop outperforms earlier published structures, exhibiting TCQ of 190ps when driving 100fF load in a 0.18μm CMOS technology.
منابع مشابه
International Journal of Research in Computer Applications and Robotics
In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...
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